The 32-bit register at 0x17E10000+0x100 only has bit 0 set when, on New 3DS, PTMSYSM:ConfigureNew3DSCPU was used with bit 1 set for the input value (the L2 cache flag). All other bits in this register are normally all-zero. Therefore, bit 0 set = new cache hardware enabled, bit 0 clear = new cache h...